Integrated circuits (ICs) are tested during fabrication to maintain device quality. Wafer acceptance testing (WAT) is one technique used to test for performance of a wafer having a plurality of ICs formed thereon. The WAT technique includes providing several test structures distributed in a peripheral region of the wafer, such as within scribe lines between ICs. During testing, a tester drives selected test structures with test signals to test different properties of the wafer, such as transistor characteristics. WAT is performed on the wafer prior to sorting and packaging of the ICs.
With WAT, since the test structures are disposed in peripheral regions of the wafer (e.g., within a scribe line), the test structures do not directly test characteristics of the ICs themselves. Typically, only a limited number of test structures are formed on the wafer (i.e., less than the number of ICs) in order to reduce testing time during manufacture. Moreover, ICs can undergo additional processing/testing steps after sorting and/or packaging, such as high-temperature operating life (HTOL) tests and the like, where it can be beneficial to further test characteristics of the ICs. WAT techniques cannot be used to test ICs once separated from the wafer.